Unified tessellation circuit and method therefor

ABSTRACT

A hardware tessellation circuit serves as a unified hardware parametric coordinate generator for providing parametric coordinates for tessellation. The tessellation circuit includes control logic that receives tessellation instruction information, such as an instruction indicating which type of multiple tessellation operations to perform, on an incoming primitive wherein the different types of tessellation include discrete tessellation, continuous tessellation and adaptive tessellation. The tessellation circuit also includes shared tessellation logic that is controlled by the control logic, and includes a plurality of shared logic units, such as arithmetic logic units, that are controllable by the control logic based on the type of tessellation detected to be used for the incoming primitive. The shared tessellation logic is controlled to reuse at least some of the logic units for two different tessellation operations defined by the tessellation type information.

RELATED APPLICATIONS

This application is a continuation of co-pending U.S. application Ser.No. 11/161,669, filed Aug. 11, 2005, entitled “UNIFIED TESSELLATIONCIRCUIT AND METHOD THEREFOR”, having as inventor Vineet Goel, owned byinstant assignee and is incorporated herein by reference, which claimspriority to U.S. Provisional Application Ser. No. 60/600,940 filed Aug.11, 2004, entitled “UNIFIED TESSELLATION CIRCUIT AND METHOD THEREFOR”,having as an inventor Vineet Goel, owned by instant assignee and herebyincorporated by reference in its entirety.

FIELD OF THE INVENTION

The invention relates generally to apparatus and methods that performtessellation on primitives such as those used in graphics processingsystems, and more particularly to apparatus and methods that performmultiple types of tessellation.

BACKGROUND OF THE INVENTION

Tessellation circuits and methods are known in graphics processingsystems to divide primitives into subprimitives represented bysubvertices. Generally, primitive tessellation can be done in threeways; these are known as discrete tessellation, continuous tessellation,and adaptive tessellation. As known in the art, tessellation may becarried out to break down a primitive, such as a quad primitive which isdefined by four vertices, triprimitives which are defined by threevertices, a line which may be defined by two vertices, or any othersuitable primitive, into smaller subprimitives in an effort to get amore accurate depiction of an outer shape of a primitive, displacementmapping, or for any other suitable purpose. For discrete tessellation,an integer tessellation level per primitive is used. For example, if aline is a primitive, and the tessellation level is one, the line isdivided into two equally spaced segments. When the tessellation level istwo, the line is broken into three segments. The level is taken from theperspective of an edge of a primitive. Similarly, a triangle issubdivided into four sub-triangles for level one tessellation.

For continuous tessellation, floating point or fractional levels oftessellation per primitive are provided so that for example atessellation level of 1.1 or 1.2 may be used to get a finer granularityof a breakdown of a primitive into smaller subprimitives. Adaptivetessellation also employs a fractional level of tessellation for eachedge of a primitive and typically includes the application of continuoustessellation to an inner portion of the primitive and a seamingtessellation at the edges of primitives. With adaptive tessellation, theprocess typically includes performing continuous tessellation bytessellating uniformly, a primitive shape within the primitive beingtessellated and applying an adaptive tessellation technique to an areaoutside the uniformly tessellated area.

Known tessellation engines are typically limited in their operation. Forexample, a typical tessellation engine may only accommodate one type ofprimitive such as a triangle primitive. In addition, tessellationengines may also typically carry out only one type of tessellation suchas discrete or continuous tessellation. However, software based adaptivetessellation techniques are also known wherein a host processor maycarry out an adaptive tessellation operation per primitive. This istypically performed since implementation of a tessellation engine inhardware can require large amounts of memory but memory is typicallylimited in graphics processors or other devices that carry out some typeof tessellation. The software adaptive tessellation approach may alsocarry out another type of tessellation namely continuous tessellation.However such known techniques typically use a forward difference methodwhich can result in holes between shared edges due to error that can begenerated utilizing the forward difference method. This can result indiscontinuous image generations. The algorithms to avoid holes betweenadjacent primitive edges tend to be complex and costly if implemented inhardware.

Since a host processor such as a CPU is required to carry out thesoftware based adaptive tessellation using the forward differencemethod, lower precision can typically result and also decrease the CPUperformance since it is required to carry out the tessellation operationto determine the tessellation vertices which may then be passed, forexample, to a graphics processor.

Accordingly, a need exists for a tessellation circuit that does notrequire a host processor to carry out tessellation vertex generation butthat would also accommodate at least all three types of tessellation.Alternatively it would be desirable to provide a tessellation circuitthat provided both continuous and adaptive tessellation but that did notunnecessarily burden a host processor in the computations, while at thesame time, minimizing the hardware cost.

BRIEF DESCRIPTION OF DRAWINGS

The invention will be more readily understood in view of the followingdescription when accompanied by the below figures and wherein likereference numerals represent like elements:

FIG. 1 is a functional block diagram illustrating one example of atessellation circuit in accordance with one embodiment of the invention;

FIG. 2 is a functional block diagram illustrating one example of atessellation circuit in accordance with one embodiment of the invention;

FIG. 3 is a flowchart illustrating one example of a method for providingprimitive tessellation in accordance with one embodiment of theinvention;

FIG. 4 is a combination of a functional block diagram and flowchartillustrating one example of a tessellation circuit in accordance withone embodiment of the invention;

FIG. 5 is a functional block diagram illustrating one example of ashared setup unit that is shared for multiple types of tessellation inaccordance with one embodiment of the invention;

FIG. 6 is a functional block diagram illustrating, one example of ashared output unit in a tessellation circuit in accordance withembodiment of the invention;

FIG. 7 is a diagram illustrating a tessellated quad primitive that hasbeen tessellated using an adapted tessellation technique;

FIG. 8 is a functional block diagram illustrating an example of anapparatus that provides tessellation in accordance with one embodimentto the invention; and

FIG. 9 is a table illustrating an example of parametric coordinateoutput information output by a tessellation circuit in accordance withone embodiment of the invention.

DETAILED DESCRIPTION OF THE INVENTION

Briefly, a hardware tessellation circuit serves as a unified hardwareparametric coordinate generator for providing parametric coordinates fortessellation. The tessellation circuit includes control logic thatreceives tessellation instruction information, such as an instructionindicating which type of tessellation to perform on an incomingprimitive wherein the different types of tessellation include discretetessellation, continuous tessellation, and adaptive tessellation. Thetessellation circuit also includes shared tessellation logic that iscontrolled by the control logic and includes a plurality of shared logicunits, such as arithmetic logic units, that are controllable by thecontrol logic based on the type of tessellation detected to be used forthe incoming primitive. The shared tessellation logic is controlled toreuse at least some of the logic units for two different tessellationoperations defined by the tessellation type information. Thetessellation circuit can tessellate multiple different primitive types,such as lines, triangles, quad primitives, line patches, tri patches andrectangular patches. The tessellation circuit also generates associatedparametric coordinates such as subprimitive coordinates in parametricspace, for different types of tessellation wherein the different typesof tessellation include, in one example, discrete tessellation,continuous tessellation, and adaptive tessellation. The generatedsubprimitive coordinates are then passed through a vertex shader orother suitable processing logic which computes the tessellation verticesfor a desired patch or primitive.

In one embodiment, the shared tessellation logic includes set-up logic,edge walker logic, and output logic, wherein hardware in the set-uplogic, such as ALUs, and hardware in the output logic, such as ALUs, arere-used for multiple different tessellation types. In addition, thestate machine in the edge walker logic may share similar states formultiple different tessellation types. Accordingly, a more robusthardware tessellation engine is provided that operates on multipleprimitive types and provides different tessellation operations whilereusing some hardware to reduce costs and provide efficient operation.Other advantages will be recognized of ordinary skill in the art.

FIG. 1 is a block diagram illustrating one example of a tessellationcircuit 10 which includes shared tessellation logic that is reused fordifferent tessellation operation types. The tessellation circuit 10receives signals specifying primitive type 12, tessellation level andtessellation type 14 and primitive vertex indices 16. The primitive typedata 12 indicates the type of primitive for which parametric coordinatesare desired. Examples of primitive types include lines which may bedefined, for example, by the index data 16 representing two indices;triangles represented by index data 16 having three indices; quadprimitives having four indices; line patches having one index; tripatches defined by 1 index; and rectangular patches also identified byone index. For lines, triangle, and quad primitive types, indicesindicate the address or pointer where vertex data is stored. For line,rect and tri patches, one index is a pointer to number of vertex indicesdescribing line, rect and tri patches. The tessellation type data 14 isprovided for each primitive or object of interest and again may beembedded as part of the tessellation signals identifying what type oftessellation should be applied to a given primitive or object. In thisexample, the tessellation type data 14 represents one of three differenttessellation types, namely, discrete tessellation which uses an integertessellation per primitive, continuous tessellation which uses floatingpoint tessellation per primitive, and adaptive tessellation whichutilizes a tessellation level per edge of a primitive. The indices datarepresents, for example, the primary vertex information or pointers tothe primary vertex information.

The tessellation circuit 10 also receives tessellation level data 18which may be user selected through a suitable software driver orprogrammed into a register (not shown) which indicates the level oftessellation desired. For example, if the tessellation type is discretetessellation, the tessellation level could be an integer such as 1, 2,3, 4, etc. If the tessellation type data 14 indicates that continuoustessellation is to be applied to the given primitive, the tessellationlevel may indicate a floating point tessellation level per primitive,such as 1.2, 1.4, 3.2, or any other suitable floating point value. Foradaptive tessellation one tessellation level per edge is sent to thetessellation engine.

The tessellation circuit 10 produces subprimitive parametric coordinates20 for use by a tessellation vertex determinator. Depending upon thetype of primitive, the parametric coordinates may be barycentriccoordinates (UVW), UV coordinates or U coordinates or any other suitableparametric coordinates for the subprimitives. If desired, thetessellation circuit 10 may also produce reordered indices 22 that maybe reordered for avoiding holes between edges of adjacent primitives.When the primitive type is a patch primitive (line, tri or rectpatches), the tessellation circuit may also output quad identificationdata 24, which is used in reordering indices of patches in theevaluation shader.

The subprimitive coordinates 20 are produced in parametric space and arepassed to, in one example, shader pipes, so the shader pipes candetermine subtriangle vertice information in XYZ space. As such, thequad identification data 24 is a subquad identifier, which identifies asubquad primitive in the larger primitive identified by indices data 16.The quad id is used reordering indices of patches in order to avoidholes between two adjacent patches. The tessellation circuit 10 isimplemented in hardware to effect a unified hardware parametriccoordinate generator.

FIG. 2 is a functional block diagram illustrating one example of thetessellation circuit 10 which includes control logic 200 that receivesthe tessellation type data 14 from an incoming instruction or othersource, and generates control data 202 for shared tessellation logic 204to control the shared tessellation logic 204 to carry out one ofmultiple tessellation operations based on the tessellation type data 14.The shared tessellation logic 204 performs parametric coordinategeneration to generate the parametric coordinate data 20 and other dataas noted in FIG. 1. As such, the control logic 200 receives tessellationinstruction information 14 and determines one of a plurality ofdifferent types of tessellation to be performed on an input primitiveidentified, for example, by the indices data 16 and primitive type data12.

The control logic 200 may be any suitable logic that performs thefunctions described herein. Shared tessellation logic 204 is controlledby the control data 202 from the control logic 200 based on the type oftessellation detected to be used for the incoming primitive. The sharedtessellation logic 204 reuses at least some logic units for multipledifferent tessellation types. For example, the shared tessellation logic204 performs both continuous tessellation and adaptive tessellationoperations and as such shares some of the same logic units for bothtypes of tessellation.

FIG. 3 illustrates one example of a method for tessellating primitivesthat is carried out, for example, by the tessellation circuit 10 shownin FIG. 1 or any other suitable structure. As shown in block 300, themethod includes analyzing tessellation type data 14 associated with atessellation instruction for an input primitive wherein the tessellationtype data 14 may represent one of at least discrete tessellation,continuous tessellation and adaptive tessellation. As shown in block302, the method also includes controlling shared tessellation logic 204that includes a plurality of shared logic units. Controlling sharedtessellation logic 204 is based on a type of tessellation detected to beused for the incoming primitive in order to reuse at least some of thelogic units for at least two different tessellation types. The processthen ends and begins again when a new primitive is to be tessellated. Assuch, this method may be carried out on a per primitive basis.

FIG. 4 is a combination of a block diagram and flow chart illustratingone example of the tessellation circuit 10 which includes set-up logic400, walker logic 402, and output logic 404. The set-up logic 400 andthe output logic 404 include some logic units that are reused forcarrying out different tessellation operations for multiple tessellationtypes. In addition the walker logic 402, which in this example is astate machine, reuses some states for both continuous tessellation andadaptive tessellation operations.

The set-up logic 400 may be any suitable logic and computes Delta_U andDelta_V data based on one or more lookup tables. Delta_U and Delta_V aresegments of a primitive in the UV coordinate space. The set-up logic 400also computes the number of segments (NUM_Segments) in the UV directionsfor a given edge of a primitive. In addition, the set-up logic 400computes the number of segments for an inner quad primitive for adaptivetessellation. Sections of the set-up logic are reused for alltessellation types and primitive types.

The hardware reused is look up table, computing delta_u and delta_v andnum_segments. An example of this is shown in the attached diagram (i),(ii) and (iii) in the TE spec.

The set-up logic 400 provides the number of segments data 406 to thewalker logic 402 along with primitive type and tessellation type.

The walker logic 402 as shown in block 408, includes logic thatdetermines the number of quads in a given primitive type. For example,if a triangle is the primitive type the walker logic determines thenumber of quads in such primitive being 3. The setup logic 400 alsocomputes the number of segments for an inner quad, for example, whereadaptive tessellation is required.

For example, referring to FIG. 7, an inner quad 700 may be determinedfor an adaptive tessellation type in a similar manner as done forcontinuous tessellations. In this example, the inner quad tessellationin u,v direction is determined by minimum tessellation level in u and vdirection. The outer window of the inner quad may be tessellated usingadaptive tessellation as shown by the angled lines wherein a quad istessellated using multiple sub-triangles. As such, a two pass adaptivetessellation operation may be performed. However, any suitable techniquemay also be used. One example is described in co-pending applicationentitled METHOD AND APPARATUS FOR DUAL PASS ADAPTIVE TESSELLATION, Ser.No. 10/790,952, incorporated herein by reference.

Referring back to FIG. 4, as shown in block 410, the walker logic alsodetermines the tessellation type as one of three types based on thetessellation type data. If the tessellation type is discrete, the walkerlogic generates the UVW for a triangle primitive and as shown in block412 it may output the UVW reordered indices to the output logic.

The logic that carries out block 408 may be shared and reused for alltessellation types such as the states that control the determination ofthe quads for a given primitive type or compute the number of segmentsfor an inner quad. As shown in block 414, if the tessellation type dataindicates a continuation tessellation is to be performed, the walkerlogic processes inner quads by representing them in three states andsets V, for the UV equal to zero for line primitives. The resultingoutputs are the UV reordered indices and any quad identifiers for patchprimitive types.

Referring to block 416, if adaptive tessellation has been indicated bythe tessellation type data 14, the walker logic processes horizontalstrips of the primitive and as shown in block 418 processes verticalstrips of the primitive that are outside the inner quad. For example, asshown in FIG. 7 the horizontal strip may be represented as 702 and avertical strip may be represented for example, as 704. As shown in block414, the walker logic then processes the inner quad 700. The states thatcontrol this process are shared for both adaptive and continuoustessellation since adaptive tessellation uses a continuous tessellationoperation for an inner quad.

The output logic 404 multiplies the UV coordinates from walker unit withthe Delta_U and Delta_V values to compute actual u,v, parametriccoordinate within a primitive for a sub-vertex. If the triangle or tripatch primitive type is used, u,v coordinates are converted to (r, s, t)coordinates which represent barycentric coordinates for a sub-vertexwithin a triangular primitive. It also discards the V data for lineprimitive types and arranges output in a format acceptable by laterprocessing such as a shader pipe which determines the vertices of thesubprimitives identified by the parametric coordinates.

FIG. 5 illustrates one example of the set up unit 400 as including afloating to fixed point converter 500 which converts incoming floatingpoint tessellation levels 18 to fix point representations and in thisexample uses 4 bits for this designation. The set up unit 400 alsoincludes a look up table 502 and an associated logic to compute theDelta U and Delta V values on a per edge basis and a number of segmentsper edge using the look-up table as known in the art. The lookup table502 consists of 1/x value for a given integer level tessellation x. Forfloating point tessellation level such as x.f, its reciprocal iscomputed using (1/x)*(1−f)+1/(x+1)*f where 1/x and 1/(x+1) are read fromlookup table. The resulting Delta values and number of segments and, ifdesired, whether the primitive is non-uniform or whether thetessellation is non-uniform, such as in the case of adaptedtessellation, is passed to the walker logic.

FIG. 6 is a block diagram illustrating one example of the output logic404, which includes index reordering logic 600 and a barycentriccoordinate generator 602. The index reordering logic 600 uses thetessellation type data 14, primitive type data 12 and whether or notthere are sub-quads to reorder indexes if for example, indices areshared with neighboring sub-primitives. The barycentric coordinategenerator 602, generates barycentric coordinates UVW for tri-primitivetypes using s and t coordinates coming from walker unit, shown as 608and 610 as provided by the walker logic. The index reordering logic at600 is reused for both continuous and adaptive tessellation types forexample. Likewise the barycentric coordinate generator may be reused forgenerating barycentric coordinates for triangular primitive types forall tessellation types. Accordingly this is additional hardware that isreused for multi tessellation types.

As such the setup logic and output logic each include logic units suchas index reordering logic, barycentric coordinate generation logic, fixto floating point converting logic or any other desired logic that iscontrollable by control logic based on the type of tessellation detectedto be used for the incoming primitive so that logic is reused.

The setup logic includes interpolators for computing delta_u anddelta_v, using values from the lookup table. Such interpolators are usedfor all the primitive types and tessellation types. The sharedtessellation logic produces barycentric coordinate data or reorderedvertex indice data and quad primitive identification data depending uponthe type of incoming primitive. The edge walker logic includes a statemachine that carries out the operations shown in the flow chart in FIG.4. The processing of inner quads and the determination of the number ofquads in a given primitive type or comparing the number of segments forinner quads are states that are shared for continuous and adaptivetessellation operations.

FIG. 8 is a block diagram illustrating one example of an apparatus thatemploys the tessellation logic 10 wherein the apparatus may be forexample a graphics processor, or other suitable graphics processingcircuit. Accordingly, apparatus 800 may be integrated on a die ifdesired. The apparatus 800 includes the pixel/vertex shader 802 thatreceives the parametric coordinate information 20 and the reorderedindice information 22 to compute tessellation vertices for variouspatches, as known in the art. The vertex shader 802 may be any suitablelogic capable of computing tessellation vertices based on theinformation provided by the tessellation logic 10. As shown in thisfigure, a rasterizer 804 may receive primitive connectivity information805 in which primitives are connected to one another so that therasterizer may then organize the information for storage in memory 806which then gets retrieved for display on a suitable display device.

FIG. 9 is a table illustrating the different modes of operationdepending upon the primitive type and the output or subprimitivecoordinates in parametric space that are output by, for example, theaforedescribed tessellation circuit 10. This table indicates how manycycles it takes to output a sub-vertex parametric coordinate(s). Since,in one example the tessellation engine interface to shader pipes islimited to 96-bits, only 3 32-bits values can be sent in one cycle. Forexample for a line primitive, tessellation will send i0, i1 and u, wherei0, i1 are indices and u is a parametric coordinate for a line. Sincethese are 3 32-bit values, such information will be passed in one cycleto the shader pipe. For a primitive type triangle, i0, i1, i2, u, v, ware issued by a tessellation engine. These are 6 32-bits values andhence will take 2 cycles to send to the shader pipe. As such, thetessellator output shown in FIG. 9 is then provided, for example, to thevertex shader 802 or other suitable processing device to compute thetessellation vertices for the subprimitives. These vertices are thendetermined in, for example, XYZ coordinate space.

The above detailed description of the invention and the examplesdescribed therein have been presented for the purposes of illustrationand description only and not by limitation. Also, the word “coupled”means directly or indirectly coupled to facilitate operation of thecircuit. It is therefore contemplated that the present invention coverany and all modifications, variations or equivalents that fall withinthe spirit and scope of the basic underlying principles disclosed aboveand claimed herein.

1. A tessellation circuit comprising: (a) control logic operative todetermine which one of a plurality of different types of tessellationprocesses are to be performed on an input primitive; and (b) sharedhardware tessellation logic, controlled by the control logic, andincluding a plurality of shared hardware logic units that are reusablefor different types of tessellation processes, wherein the sharedtessellation hardware logic is operative to reuse at least one of theshared hardware logic units for at least two different types oftessellation processes.
 2. The tessellation circuit of claim 1 whereinthe different tessellation process types include at least two of thefollowing: discrete tessellation, continuous tessellation, and adaptivetessellation.
 3. The tessellation circuit of claim 1 wherein the sharedhardware logic units include at least setup logic, walker logic, andoutput logic, each comprising logic units that are controllable by thecontrol logic.
 4. The tessellation circuit of claim 3 wherein the setuplogic includes interpolators that are reused for both adaptive andcontinuous tessellation types and wherein the tessellation circuitproduces parametric coordinates for use in determining subprimitivevertices.
 5. The tessellation circuit of claim 3 wherein the sharedhardware tessellation logic is controlled by the control logic togenerate parametric coordinate data for all of the different types ofprimitives from the group of lines, triangles, quad primitives, linepatches, tri patches, and rectangular patches.
 6. The tessellationcircuit of claim 3 wherein the shared hardware tessellation logicproduces at least one of: barycentric coordinate data, reordered vertexindice data, and quad primitive identification data depending upon atype of incoming primitive.
 7. The tessellation circuit of claim 3wherein the walker logic is comprised of a state machine and whereinstates of the state machine are shared for continuous and adaptivetessellation operations.
 8. A method for tessellating primitivescomprising: controlling shared hardware tessellation logic to reuse atleast one of a plurality of shared hardware logic units for at least twodifferent tessellation process types.
 9. The method of claim 8comprising determining which one of a plurality of different types oftessellation processes to be performed on the input primitive; andwherein the different types of tessellation include at least one of thefollowing: discrete tessellation, continuous tessellation, and adaptivetessellation.
 10. The method of claim 8 wherein the method includesreusing interpolators for both adaptive and continuous tessellationtypes and wherein the tessellation circuit produces parametriccoordinates for use in determining subprimitive vertices.
 11. The methodof claim 8 wherein the method includes generating coordinate data forall of the different types of primitives from the group of lines,triangles, quad primitives, line patches, tri patches, and rectangularpatches.
 12. The method of claim 8 wherein the method includes producingat least one of: barycentric coordinate data, recorded vertex indicedata, and quad primitive identification data depending upon a type ofincoming primitive.
 13. The tessellation circuit of claim 8 wherein oneof the shared logic units is an edge walker comprised of a statemachine, wherein states of the state machine are shared for continuousand adaptive tessellation operations.
 14. A method for tessellatingprimitives comprising: (a) determining which one of a plurality ofdifferent types of tessellation processes to be performed on the inputprimitive wherein the different types of tessellation include at leastone of the following: discrete tessellation, continuous tessellation,and adaptive tessellation; and (b) controlling shared hardwaretessellation logic to reuse interpolators for both adaptive andcontinuous tessellation types and wherein the method comprises producingparametric coordinates for use in determining subprimitive verticesusing the reused interpolators.